1. Field of the Invention
The present invention relates to an operation circuit for performing an operation using a subtractive shift type divide algorithm and, in particular, an operation apparatus and method using a dividing device which achieves an improvement on an operation of a signed dividend and divisor and on the method for detecting an overflow.
2. Description of the Related Art
The subtractive shift type divide algorithm, for example, is used for a divided operation, including a sign bit, which is performed on an information processing apparatus etc.--See Horikoshi "High-Speed Operation System of A Computer" issued by Kindai-Kagaku Co., Ltd. 1980--.
The subtractive shift type divide algorithm including a sign bit comprises taking the absolute value of a dividend and that of a divisor, performing an operation with the absolute values as positive numbers and determining a quotient and a remainder with the use of the signs of the dividend and divisor.
An overflow in a divide operation, that is, a state overflown beyond, for example, 16 bits is detected from the fact that a quotient cannot be represented with, for example, an unsigned 16-bit expression when a difference becomes "0" in a divide operation, dividend--(divisor.times.2.sup.16) or when no borrow occurs in a subtractive operation. The overflow in the divide operation whose quotient enters the signed bit expression is not detected until a full repeated operation is completed. For this reason, it is useless to necessarily take a one full cycle time against an exceptional event of an overflow rarely encountered. This causes a degraded operation efficiency.
In this context, the number of clocks all required in the aforementioned divide operation becomes: All the clock number
=the number of clocks required for a repeated processing.times. the number of repetitions
+the number of clocks required to find an absolute value.times.2
+the number of clocks required to correct the sign.times.2
Here a shift in a repeated processing, if being performed by an ALU (an arithmetic logic operation unit), takes 3 to 4 clocks for repetition, meaning that about a half of all the clock number for a full processing are used up by the clock number except for the repeated processing.
In the conventional system, in addition to the repeated processing, a waste time (a head) has been encountered in the divide operation, including a sign bit, such as the pre-processing and post-processing, that is, the start of a requisite repeated processing following the finding of the absolute value of a dividend and that of a divisor and finally the finding of a quotient and remainder on the basis of a sign equality. The problem with the conventional system lies in that, even if the number of clocks for each repetitive operation can be reduced with a hardware for shift processing which performs a high-speed divide operation, it is not yet possible to reduce the number of clocks for full processing, to such an extent as has been expected due to an overhead involved. It has not been possible to achieve an adequately high speed unit compatible with a hardware investment. It is important to, not only reduce a requisite time for repeated operation but also to reduce such an overhead involved.